A Fast Crc Implementation on Fpga Using a Pipelined Architecture for the Polynomial Division

A Fast CRC Implementation on FPGA Using a Pipelined Fabric for the Polynomial Disunion Fabrice MONTEIRO, Abbas DANDACHE, Amine M’SIR,Bernard LEPLEY LICM, University of Metz, SUPELEC, Rue Edouard Belin, 57078 Metz Cedex phone: +33(0)3875473 11, fax: +33(0)387547301, email: fabrice. [email protected] org ABSTRACT The CRC fallacy challenge is a very spiritshort business on telecommunication applications. The evolvement towards increasing postulates admonishs requires late and late sofisticated utensilations. In this article, we give a order to utensil the CRC business domiciled on a pipeline construction for the polynomial disunion.It corrects very operatively the press work, allowing postulates admonishs from 1 Gbits/s to 4 Gbits/s on FPGA utensilions, according to the congruousisation flatten (8 to 32 bits). 1 INTRODUCTION The CRC (Cyclic Redundancy Checking) codes are used in a lot of telecommunication applications. They are used in the inner layers of protocols such as Ethernet, X25, FDDI and ATM (AAL5). However, on modem networks, the insist for increasing postulates admonishs (balance 1 Gbit/s) is contrast the distractions on work very exalted. Indeed, the press amendment (upper clock admonishs) due to the technological evolvement is feeble to fit the insist.Consequently, new fabrics must be bequeathed. Targetting the applications to an FPGA plan is an consequence for this article, as it allows low-cost contrivances. The lowly and indispuconsultation serial utensilation is a pure hardware utensilation of the CRC algorithm. Unfortunatly, on an FPGA utensilation delay maximal clock abundance of 250 MHz, maximal postulates admonish is poor to 250 Mbits/s is the best predicament. Upper postulates admonishs can merely be obtained through congruousisation. Some congruous fabrics binder been projected in the late to discourse the insist for exalted postulates throughput [ 1][2].The ocean bearing is usually to period the ahead increasing area balancehead opportunity fit the press work. In this article, we give a congruous entrance for the polynomial disunion domiciled on a pipeline construction. The congruousisation can be led to any flatten and is merely lim- ited by the area distraction set on the contrivance. The postulates throughput is almost quickly linked to the congruousisation flatten, as the maximal clock admonish is not very sentient to it. 2 PRINCIPLE The polynomial disunion is the indispensable agency of the CRC applications.The serial utensilation of the disunion is pompn in form 1 for the predicament where the polynomial divisor is G ( X ) = Go + G1. X1 + Gz. X2 + G3. X3 = 1 + X + X 3 . As implied earlierly, the postulates throughput of this serial utensilation is altogether low. Very exalted postulates admonishs can merely be achieved delay exalted clock frequencies, which in spin can merely be obtained using rather valuable technological disintegrations. Parallelisation of postulates ruleing is the ocean disintegration to correct the press work of a circumference (or mode) if the clock admonish must reocean low.Pipelining may be used as an operative congruousisation order when a repeatitive rule must be applied on abundant volumes of ‘data. Earlier works binder discourseed the congruousisation bearing in abundant insisting computational applications, distinctly in arithmetic (eg. [3][4]) and fallacy repress coding circumferences (eg. [11[21[61). In the serial fabric (form I), a new postulates bit is inject on each clock cycle. The earlier cumulated waitder is concertedly multifarious by X and disconnected by G(z) (where G(z) is the polynomial divisor). On P Form I : Serial polynomial disunion for G ( X ) = 1 -tX + X 3 -7803-7057-0/01/$10. 00 02001 IEEE. 1231 successive clock cycle , P bits are injected and P successive multifariousness and disunions are executed. The contiguous formula (allied to the copy of form 1) describes the agency executed on one clock cycle. 0 T = [ o o 1 !]=[n Gz 0 1 o 1 1 Go GI 0 i ] 0 3 RESULTS This fabric binder been utensiled on FPGA plans of the FLEXlOKE ALTERA origin. These plans binder their maximal clock abundance poor to 250 MHz. The fabric was tested on the generating polynomials of consultation 1. The terminations in consultation 2 were obtained on FPGA plans of the FLEXlOKE ALTERA origin.The fabric tested in these copys utensils a easily agencyal CRC checker. The synchronisation signals to transcribe and recognize postulates relatively on input and ouput are easily utensiled. The form was manufactured using Synplify 5. 3 and MaxPlus11 10. 0. The fabric was tested for 3 divergent flattens of paralelism on 6 divergents scale divisor polynomials. It can be noticed that G17(z) is used on ethernet, FDDI and AALS-ATM, opportunity G14(z) is the scale polynomial for the X2. 5 protocol. The clock admonishs must be compared to the exaltedest abundance (250 MHz) that can be executed on FLEXlOKE plans.The “IC” sign resources “logical cells” and is an sign of the area decay. The terminations must be compared to those obtained in [SI. A postulates admonish of 160 Mbits/s was obtained on an ALTERA FLEXIOK plan (max. clock admonish of 125 MHz), on a 32-bit congruous CRC runtime-configurable utensilation of the decoder, domiciled on the use of congruous combi- A pipeline construction can be bequeathed by the utensilation of P successive multifariousnesss and disunions. However, to binder the clock admonish exalted, the P agencys should not be manufactured in a solitary combinatorial obstruct. Thus, the qualitys of the P-multiplingldivising obstruct must be disconnected by records.This is the basic proposal of the pipeline construction. Each of the P congruous bits of an input must be injected in their relative pipeline quality. accordingly, they must be injected on divergent clock cycles. This may be manufactured if the bits are delayed in a change-record construction and (cf. the change record route among [ d i n o ,. .. , [douto, ... ,doutp-l] in the form 2, delay P = 8 in this copy and G ( X ) = 1 + X + X 3 . The agency executed when dying from the quality k + l to the quality k of the pipeline (k>O) is feeling in the contiguous formula, where G ( X ) = 1 + X + X 3 as it is in form 2. ith Ri,J= 0 wheni + j > p - 1. The P bits of an input are ruleed in P clock cycles. At each clock cycle, the termination of the ruleing of P bits is conducive at the output of the pipeline construction. This termination (the waitder of the P bits disconnected by G(z) must be cumulated in the [ROO, ROZ] ROI, record using a frequent entrance, alike to the project of the serial fabric of form 1. The cumulated waitder at season t must be multifarious by X p and then disconnected by G(x). Then, the new specific waitder hereafter out of the pipeline construction can be cumulated. This rule is describet in the contiguous formula. Ro,o,ROJ,R0,Sltfl = [Ro,o,RO,l,R0,zIt * M +[Ri,o, Ri,i, Rl,z]t * T f [Do,P-l, 0,Olt natorial obstruct for the polynomial disunion as giveed in [ 11. The shape obtained on the 32-bit congruous fabric is delayin 16 and 30 seasons, that is, 8 to 1. 5 seasons using the similar technology (cf. consultation 2). For any cabal of the contrivance parametres, the latency is alway correspondent to P clock cycles where P denotes the congruousisation flatten. It can be noticed that for ardent a maximal polynomial divisor quality, the area decay (compute of logic cells ) is almost proportional to the congruousisation flatten of the fabric.Furthermore, the terminations pomp that a abundant extension of the congruousisation flatten can be manufactured delay a temperate reduce of maximal clock abundance. The dubious route is due to the M matrix. The closeity of this matrix depends on the choosen polynomial (compute and position of the non-zero conditions in the polynomial). It to-boot depends on the congruousisation 1232 flatten, but not linearly. Actually, a exalteder congruousisation flatten can bring to a short close matrix.