Ultrasonic Speed Measurement

“ULTRA SONIC SPEED MEASUREMENT DEVICE” A PROJECT REPORT Submitted in favoring fulfillment Of capacitys for grant of the grade Of BACHELOR OF TECHNOLOGY In ELECTRONICS & COMMUNICATION ENGINEERING By: Nimisha Sharma Nishant Tyagi Gaurav Sharma [pic] Portion of Electronics & message engineering Radha Govind Engineering College Meerut, U. P 2009-2010 ULTRA SONIC SPEED MEASUREMENT DEVICE By: Nimisha sharma Nishant tyagi Gaurav sharma [pic] Portion of Electronics & message engineering Radha govind Engineering College Meerut, U. P 2009-2010 ACKNOWLEDGEMENT Before we get in to turbid of things we would enjoy to add a few thick expression for the mob who were the deal-out-among-among of the artifice in vaporous ways. Mob who gave limitsuspend aid right from the ordain the fancy were conceived. In deal-out-amongicular, we eagerness to cheer Mr. P. K Singh Head of the Department, Electronics & Message and Mr. Abhishek Singh lecturer, Electronics & Message Portion for providing this turn to us. After doing this artifice we can confidently say that this proof would not solely possessed us after a time technical information but so has unparsed the manliness of care and desire . he attributes required nature a lucky professional. Gaurav Sharma Nimisha Sharma Nishant Tyagi CANDIDATE’S DECLARATION We, hither by proexperience that the goods which is nature presented in the artifice recital entitled Ultra sonic hurry size artifice in favoring fulfillment of the capacity for the grant of grade of BACHELOR OF TECHNOLOGY in Electronics & Message Engineering submitted in the harborion of Electronics & Message Engineering of the Institute, is an true incomeings of our own goods carried out during terminal year of B. tech grade inferior the superdesire of Mr. P. K Singh Head of the Department, Electronics & Message and Mr. Abhishek Singh lecturer, Portion Electronics & Message Artifice group:- Gaurav Sharma (0606931023) Nimisha Sharma (0606931045) Nishant Tyagi (0606931047) This is to proexperience that the aloft declaration made by the aloft candidates is emend to the best of my information. Mr. P. K Singh Mr. Abhishek Singh (H. O. D) (Lecturer) Dept. of Electronics & Comm. Dept. of Electronics & Comm. R. G. E. C R. G. E. C Meerut, U. P Meerut, U. P Date……………. Date……………. Place…………… Place…………... TABLE OF CONTENTS 1. INTRODUCTION…………………………………………………………………………... a. MEANING OF THE WORD PROJECT……………………………………………... . ABSTRACT ... …………………………………………………………………………... c. PARTS OF SPEED MEASUREMENT DEVICE……………………………………. 2. GENERAL DISCRIPTION AND FEATURES OF MICRO CONTROLLER ……………. 3. HARDWARE DISCRIPTION………………………………………………………………… a. VOLTAGE REGULATOR LM 7805…………………………………………………. b. COMPONENTS ………………………………………………………………………. 4. PCB LAYOUT ………………………………………………………………………………... a. STEPS FOR MAKING PCB ……………………………………………………….. … b. CIRCUIT LAY OUT ………………………………………………………………….. 5. SOFTWARE PROGRAM …………………………………………………………………….. 6. TESTING……………………………………………………………………………………….. 7. TROUBLESHOOTING ……………………………………………………………………….. 8. CONCLUSION………………………………………………………………………………… 9. REFERENCES…………………………………………………………………………… 10. APPENDIX…………………………………………………………………………………….. INTRODUCTION MEANING OF PROJECT The artifice profits the apprehension of the aftercited scope of engineering – P-signifies the lion of planning which deals after a time symbolic race and right ordainment of beneathneathneathstanding and prompting receptivity conformably to the needs R-it is helpmate after a time the vocable resources which guides to exalt planning . OJ-this message signifies the balancehead expenses in unestimated expenses that may engage-place in the fabrication contemplation or layout of the artifice. E- signifies the vocable engineering. C- signifies the transharbor encircling lion of fabrication low require. T-the vocable T stands for technique. probable thither is a technique; it is impracticable to thorough the artifice . The disposal thus arrived is that artifice is a irrelative suspect discussed and scheme in a deal-out-amongicular scrutiny . we can say that artifice comprises thorough capacity of means , tools , collision and needs. It considers the tour diagram and separate productional productions in posteriority and basis encircling the agent and in the terminal we can say encircling the artifice acquisition waste. CERTIFICATE This is to proexperience that Mr. GAURAV SHARMA, tyro of B. Tech (Electronics & message Engineering) Terminal year from Radha Govind Engineering College has luckyly thoroughd his artifice “ULTRA SPEED MEASUREMENT DEVICE”. During the artifice epoch he was goodsing inferior the govern of Mr. Abhishek Singh (lecturer, Electronics & Message Engineering Department). His production during the artifice has been Excellent. We eagerness him all the best for his coming. Mr. P. K Singh Mr. Abhishek Singh (H. O. D) (Lecturer) Electronics & Comm. Dept. Electronics & Comm. Dept. R. G. E. C R. G. E. C Meerut, (U. P) Meerut, (U. P) CERTIFICATE This is to proexperience that Ms. NIMISHA SHARMA, tyro of B. Tech (Electronics & message Engineering) Terminal year from Radha Govind Engineering College has luckyly thoroughd her artifice “ULTRA SPEED MEASUREMENT DEVICE”. During the artifice epoch she was goodsing inferior the govern of Mr. Abhishek Singh (lecturer, Electronics & Message Engineering Department). Her production during the artifice has been Excellent. We eagerness her all the best for her coming. Mr. P. K Singh Mr. Abhishek Singh (H. O. D) (Lecturer) Electronics & Comm. Dept. Electronics & Comm. Dept. R. G. E. C R. G. E. C Meerut, (U. P) Meerut, (U. P) CERTIFICATE This is to proexperience that Mr. NISHANT TYAGI, tyro of B. Tech (Electronics & message Engineering) Terminal year from Radha Govind Engineering College has luckyly thoroughd his artifice “ULTRA SPEED MEASUREMENT DEVICE”. During the artifice epoch he was goodsing inferior the govern of Mr. Abhishek Singh (lecturer, Electronics & Message Engineering Department). His production during the artifice has been Excellent. We eagerness him all the best for his coming. Mr. P. K Singh Mr. Abhishek Singh (H. O. D) (Lecturer) Electronics & Comm. Dept. Electronics & Comm. Dept. R. G. E. C R. G. E. C Meerut, (U. P) Meerut, (U. P) CHAPTER 1 ABOUT OUR PROJECT Our artifice the ultrasonic hurry size artifice is used to appraise hurry of a bearing emotional in sumenance of it using ultrasonic prospers. The concept of using ultrasonic prospers instead of any other communicating tools as infrared and RF is its lofty formalness and very suspend interlocution by the enclosing. Thither can separate methods that can be opted to contemplation this agent such as Doppler Goods etc. but we bear used the concept of removal size at a recognized space-between. The pulse is nature pestilential at a recognized space-betwixt and the selfsame removal is appraised of the two pulses. The dissonance in the removals is observed and is then severedd by the term protraction betwixt the two pulses. As upshot the selfsame hurry is allureed. The dispose of this artifice is undeviatingly subject on the production of the transmitter and the receiver. Reform the transmitting and receiving reckon melioscold earn be its dispose. Mathematical segregation(hypothetical) The protraction of pulse is 5 milliseconds. The removal for the conspicuous1 be say 3 cm. The removal for the conspicuous2 be say 2. 95 cm. Dissonance of removals is (3-2. 95) = . 05 cm. Hurry = removal/ term Hurry = . 05/5 = 10 meters/sec ADVANTAGE AND DISADVANTAGE The leading customs of our artifice are One of the leading customs our artifice is its multi custom. It can be used as 1 Hurry size 2 Removal size 3 Car parking master The other custom of this artifice is its require. Its require is suspend than 1000 INR. The formal upshot is one balance custom of our artifice. Limitation of our artifice. The leading discustom of our artifice is its dispose. Due to the use of low reckon transmitter and receiver. Lofty reckon transmitter and receiver profit loftyer dispose of upto 10 to 15 mtrs Block diagram [pic] Tour diagram Agoing In our artifice Ultrasonic Hurry Size Artifice we are going to appraise the hurry of a emotional bearing. For this we are using the Ultrasonic Sensors. We leading engender a 40 KHz conspicuous by taking the term epoch of 25 microseconds. Then we really engender the pulse shiver after a time a stoppage of 5 milliseconds. For this we programmed the microcontroller. We transmit the pulse by urgent-compulsory the switch that is aaffect to the pin no. 1 of the microcontroller. At this relieve the removal of the aim from the artifice is appraised and is stored in the microcontroller. Then after the stoppage of 5 milliseconds the relieve pulse hits the emotional aim. Again the removal of the aim is appraised and is stored in the microcontroller. Then we can abundantly furnish out the dissonance in the removal by singly subtracting these two removals. Now we bear the removal and so the term. Therefore by the formula hurry = removal / term we can furnish out the hurry of the emotional aim. In the transmitter deal-out-among-among we bear LM311which is a voltage comparator and is used hither as the nicety balancer whose pin no. 2 is aaffect to the pin no. 2 of the microcontroller. Then at pin no. 7 and pin no. 8 the ultrasonic transmitter is placed. In the receiver deal-out-among-among we bear LM833 for dilution and 74HC14N as the Hex inverting Schmitt trigger. The pin no. 1 of 74HC14N is aaffect to the pin no. of LM833. The ultrasonic receiver is aaffect betwixt pin no. 6 of LM833 and cause. These ultrasonic transmitter and receiver are placed suspend to each other so that thither earn be restriction rattle. Why ultrasonic conspicuous ? 'ULTRA'-sonic is a probe prosper after a time a reckon aloft the usual dispose of civilized inclineing. Most civilizeds can incsuccession up to 16,000 Hertz. Young mob can incsuccession almost to 20,000 Hertz. Bats and mice and other mean critters can incsuccession greatly loftyer and use those probes to 'see' the universe encircling them. An ultrasonic imaging artifice transmits a conspicuous into a balance and then listens for the mirrored prospers. The balance receiving transducers you use to prime up the probe the melioscold you can divulge what you are 'looking' at. Reflected prospers earn penetscold one receiver antecedently the next domiciled on whither the meditation aim is located. Electronics are urban sufficient to state the superscription and removal to the mirrored aims. So the loftyer the reckon you profusely the melioscold decomposition you earn see. A computer is interfaced after a time an deck of receiving tranceducers and it calculates the superscription and removal that the frequent answers must reproduce-conduct and then it plots the paint of the upshots. The Image can be displayed or printed. In ultrasonic non baleful experienceing, lofty-reckon probe vibrations are pestilential into embodied by an ultrasonic transducer. The experience agent then analyzes the ultrasonic conspicuouss which are vulgar using either a pulse-answer or through-transmission method. In the pulse-answer command, the transmitting transducer so serves as the ultrasonic receiver and analyzes the mirrored conspicuous after a time relation to richness and term. In the through-transmission command, the ultrasonic conspicuous is vulgar by a severed transducer which analyzes the richness waste of conspicuous. These ultrasonic NDT methods earn evidence embodied defects such as covetitudinal and across cracks, inclusions and others as courteous-mannered-mannered-mannered as ID/OD work and dimensional changes such as turbidness and ovality. Components Component required 1. Ultrasonic Transmitter and Receiver 2. Resistor 3. Capacitor 4. Crystal 5. Preset 6. Switch 7. LCD 8. Ability Contribute 9. IC’s • LM833 • LM311 • 74HC14N • 7805 10. Micro master • AT89S52 11. Wires 12. Shiver Strip 13. IC Base Specification ULTRASONIC SENSORS [pic] Excerption and use of ultrasonic ceramic transducers : The scope of this collision hush is to aid the user in the excerption and collision of the Ultrasonic ceramic transducers. The public transducer contemplation features a piezo ceramic disc bender that is resounding at a professed reckon of 20 – 60 KHz and radiates or receives ultrasonic temper. They are voicelessnessd from the piezo ceramic audio transducer in that they profit probe prospers aloft 20 KHz that are muttering to civilizeds and the ultrasonic temper is radiated or vulgar in a proportionately limited glow. The “open” image ultrasonic transducer contemplation exposes the piezo bender bonded after a time a metal conical cone after a protective ward. The “enclosed” image transducer contemplation has the piezo bender mounted undeviatingly on the inferiorside of the top of the circumstance which is then machined to resounding at the desired reckon. The “PT and EP” image transducer has balance inner damper for minimizing “ringing”, which usually works as a transceiver – unsettled in a incomprehensive epoch and then switching to receiving command. Comparative characteristics : When compared to the enclosed transducer, the known image receiver earn lay-known balance electrical output at a profitn probe hurry raze (lofty sensitivity) and conduct suspend diminution in output as the known reckon deviates from usual resounding reckon (superior bandwidth). The known image transmitter earn profit balance output for a unfair press raze (balance fruitful). The enclosed image transducer is contemplationed for very dusty or outdoor collisions. The sumenance of the transducer must be kept neat and exempt of hurt to obviate wastees. The transmitter is contemplationed to bear low impedance at the resounding reckon to allure lofty habitual achieveingness. The receiver is affected to maximize the impedance at the bounded anti-resounding reckon to yield lofty electrical achieveingness. Probe propagation : In ordain to rightly prime a transducer for a profitn collision, it is leading to be conscious of the principles of probe propagation. Since probe is a prosper lion, its propagation and directivity are kindred to its prosperlength (? ). A usual radiation ability archemark for either a generator or receiver of prospers is shown in Shape 1. Due to the reciprocation of transmission and admittance, the graph harborrays twain ability radiated acovet a profitn superscription (in circumstance of prosper product), and the sensitivity acovet a profitn superscription (in circumstance of prosper admittance). As an issue of a usual predicament, a transducer of 400ET250 has an telling transection of 23 mm (1mm respect turbidness) earn profit a deep glow (-6dB) after a time ample width of 30° at a reckon of 40 KHz. For known image transducers, the glow is unwavering by the curved and transection of conical cone secure on the bender insidely of housing and the knowning transection so it can not be singly conducive by the transection of the housing. The concentration of probe prospers retrench after a time the removal from the probe commencement, as rule be expected for any prosper lion. This retrench is leading a combirace of two goodss. The leading is the inverse balance law or spherical dissipation in which the concentration fall 6dB per removal embraced. This scold is vulgar to all prosper phenomena regardsuspend of reckon. The relieve goods causing the concentration to retrench is the parching of the prosper by the air (see shape 2). Parching goodss dissimilate after a time dampness and dust resigned of the air and most leadingly, they dissimilate after a time reckon of the prosper. Absorption at 20 KHz is encircling 0. 02dB/30 cm. It is evident that inferior frequencies are melioscold advantageous for covet dispose propagation. Of road, the excerption of a inferior reckon earn upshot in suspend directivity (for a profitn transection of commencement of receiver). [pic] How far the transducer could penetrate? One of the most regularly asked scrutinys is “How far the transducer could penetrate? ”. This scrutiny can be answered by a unadorned reckoning that is domiciled on the published unfairations in the Ultrasonic Ceramic Transducer Basis Sheets. The basic process is to leading state the restriction probe hurry raze lay-opened at the sumenance end of the receiver for a unfair transmitter driving voltage and removal betwixt the transmitter and receiver (transceiver has embrace removal betwixt mirror target). This SPL must then be converted “Pa” (Pascal) or “? bar” (microbar) units. The sensitivity of the receiver must then be converted from a dB relation to an independent mV/Pa or ? bar raze resist to allure the terminal output. Assume a 400ST160 transmitter is pressn at a raze of 20Vrms and a 400SR160 receiver is located 5 meters from the ransmitter and loaded after a time a 3. K Ohm resistor (loaded resistor compute varies receiver sensitivity, gladden see “Acoustic Performance” of transducer basis prevarication). The segregation is indispensable to the indispensable inferiorstanding of the leadings of probe prosper propagation and competition but it is dilatory. The shape 10 beneath is a graphical reproduce-exhibitation of anterior segregation which may be used uniformly in the SPL at the receiver is stated. Enter the graph from the SPL axis and income upward to an intersection after a time –dB sensitivity raze of the receiver using the 1V/? bar relationd basis. Follow a spiritnear succession to the “Y” axis to allure the receiver output in V. At Receiver Ultrasonic answer ranging : Ultrasonic ranging methods are used to state the removal to an aim by measuring the term required for an ultrasonic prosper to wandering to the aim and repay to the commencement. This technique is regularly referred to as “answer ranging”. The removal to the aim may be kindred to the term it earn engage for an ultrasonic pulse to expand the removal to the aim and repay to the commencement by dividing the whole removal by the hurry of probe which is 344 meters/relieve or 13. 54 inches/millisecond. IC’s [pic] BASIC OF LM833 Low rattle dual productional amplifier It is a monolithic dual productional amplifier deal-out-amongicularly courteous-mannered-mannered-mannered advantageous for audio collisions. It Offers low voltage rattle (4. 5nV/vHz) and lofty reckon productions (15MHz Gain Bandwidth Product, 7V/? s slew scold). In attention the LM833 has so a very low distortion (0. 002%) and laudable phase/gain margins. [pic] TOP VIEW AND PIN SET [pic] Features of LM833 • LOW VOLTAGE NOISE: 4. 5nV/vHz • HIGH GAIN BANDWIDTH PRODUCT: • 15MHz • HIGH SLEW RATE: 7V/? s • LOW DISTORTION: 0. 002% • EXCELLENT FREQUENCY STABILITY • ESD PROTECTION 2kV Basic of LM311 The LM111 sequence are voltage comparators that bear input bearings approximately a hundred terms inferior than artifices enjoy the mA710. They are contemplationed to opescold balance a stray dispose of contribute voltages; from criterion ±15 V op amp eatables down to a separate 3 V contribute. Their output is consonant after a time RTL, DTL, and TTL as courteous-mannered-mannered-mannered as MOS tours. Further, they can press lamps or relays, switching voltages up to 50 V at bearings as lofty as 50mA. Twain the inputs and the outputs of the LM111 sequence can be incomplex from method cause, and the output can press loads referred to cause, the unequivocal contribute, or the disclaiming contribute. Offset balancing and strobe capacity are yieldd and outputs can be wire-ORed. Although sinferior than the mA710 (200 ns exculpation term versus 40 ns), the artifices are so greatly suspend bent to supposititious oscillations. [pic] TOP VIEW AND PIN SET [pic] features FEATURES • Operates from separate 3 V contribute (LM311B) • Maximum input prejudgment bearing: 150 nA (LM311: 250 nA) • Maximum offset bearing: 20 nA (LM311: 50 nA) • Differential input voltage dispose: ±30 V • Ability consumption: 135 mW at ±15 V • Lofty sensitivity: 200 V/mV • Naught crossing guide 7805 The 7805 sequence of three-terminal unequivocal regulator are suited in the TO-220/D-PAK bundle and after a time separate urban output voltages, making them serviceable in a broad dispose of collisions. Each image employs inner bearing limiting, blood-warm preclude down and unendangered known area security, making it essentially imperishable. If extensive excitement waning is yieldd, they can liberate balance 1A output bearing. Although contemplationed primarily as urban voltage regulators, these artifices can be used after a time superficial components to allure adjustable voltages and bearings. [pic] 1 2 3 [pic] Inner diagram [pic] Features • Output Floating up to 1A Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V • Blood-warm Overload Security • Incomprehensive Tour Security • Output Transistor Unendangered Known Area Security 74HC14N HEX SCHMITT TRIGGER INVERTER Basic of 7414 Each tour functions as an inverter, but owing of the Schmitt action, it has opposed input threshold razes for unequivocal (VT+) and for disclaiming going(Vt-) conspicuouss. These tour are temperature compensated and can be triggered from the slowest Micro master AT89S52 Basic of AT89S52 The AT89S52 is a low-power, lofty-production CMOS 8-bit micromaster after a time 8K bytes of in-method programmable Flash retention. The artifice is fabricationd using Atmel’s lofty-density nonvolatile retention technology and is consonant after a time the industry- criterion 80C51 information set and pinout. The on-morsel Flash allows the program retention to be reprogrammed in-method or by a customary nonvolatile retention programmer. By combining a multigenous 8-bit CPU after a time in-method programmable Flash on a monolithic morsel, the Atmel AT89S52 is a abilityful micromaster which yields a loftyly-flexible and require-telling answer to frequent embedded govern collisions. The AT89S52 yields the aftercited criterion features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O successions, Watchdog termr, two basis pointers, three 16-bit termr/counters, a six-vector two-raze hinder architecture, a ample duplex serial harbor, on-morsel oscillator, and clock tourry. In attention, the AT89S52 is contemplationed after a time static logic for production down to naught reckon and aids two software primeable ability saving commands. The Idle Command stops the CPU time allowing the RAM, termr/counters, serial harbor, and hinder method to remain functioning. The Power-down command saves the RAM resigneds but exemptzes the oscillator, disabling all other morsel functions until the next hinder or hardware reset. [pic] Features of AT89S52 • Consonant after a time MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Retention – Endurance: 1000 Write/Erase Cycles • 4. 0V to 5. 5V Known Dispose • Fully Static Operation: 0 Hz to 33 MHz • Three-raze Program Retention Lock • 256 x 8-bit Inner RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Hinder Sources • Ample Duplex UART Serial Channel • Low-ability Idle and Power-down Modes • Hinder Recovery from Power-down Command Watchdog Timer • Dual Basis Pointer • Power-off Flag • Urban Programming Term • Flexible ISP Programming (Byte and Page Mode) Coding ; succession 1 ; #comprise CLINE0 ; end of succession 0 ; succession 1 ; /* CLINE1 ; end of succession 1 ; succession 2 ; SFR31. H CLINE2 ; end of succession 2 ; succession 3 ; Copyright 1995 SPJ Systems, Pune CLINE3 ; end of succession 3 ; succession 4 ; CLINE4 ; end of succession 4 ; succession 5 ; This header finish contains SFR declarations for the CPU 8031 CLINE5 ; end of succession 5 ; succession 6 ; Gladden hush that you earn bear to comprise SFR31. H in your program, if you CLINE6 ; end of succession 6 ; succession 7 ; eagerness to approximation the SFRs from your C program. CLINE7 ; end of succession 7 succession 8 ; */ CLINE8 ; end of succession 8 ; succession 9 ; CLINE9 ; end of succession 9 ; succession 10 ; SFRACC0xe0 CLINE10 ACCequ0e0h ; end of succession 10 ; succession 11 ; SFRREG_B0xf0 CLINE11 REG_Bequ0f0h ; end of succession 11 ; succession 12 ; SFRPSW0xd0 CLINE12 PSWequ0d0h ; end of succession 12 ; succession 13 ; SFRSP0x81 CLINE13 SPequ081h ; end of succession 13 ; succession 14 ; SFRDPL0x82 CLINE14 DPLequ082h ; end of succession 14 ; succession 15 ; SFRDPH0x83 CLINE15 DPHequ083h ; end of succession 15 ; succession 16 ; SFRP00x80 CLINE16 P0equ080h ; end of succession 16 ; succession 17 ; SFRP10x90 CLINE17 P1equ090h ; end of succession 17 ; succession 18 ; SFRP20xa0 CLINE18 P2equ0a0h ; end of succession 18 ; succession 19 ; SFRP30xb0 CLINE19 P3equ0b0h end of succession 19 ; succession 20 ; SFRIP0xb8 CLINE20 IPequ0b8h ; end of succession 20 ; succession 21 ; SFRIE0xa8 CLINE21 IEequ0a8h ; end of succession 21 ; succession 22 ; SFRTMOD0x89 CLINE22 TMODequ089h ; end of succession 22 ; succession 23 ; SFRTCON0x88 CLINE23 TCONequ088h ; end of succession 23 ; succession 24 ; SFRTH00x8c CLINE24 TH0equ08ch ; end of succession 24 ; succession 25 ; SFRTL00x8a CLINE25 TL0equ08ah ; end of succession 25 ; succession 26 ; SFRTH10x8d CLINE26 TH1equ08dh ; end of succession 26 ; succession 27 ; SFRTL10x8b CLINE27 TL1equ08bh ; end of succession 27 ; succession 28 ; SFRSCON0x98 CLINE28 SCONequ098h ; end of succession 28 ; succession 29 ; SFRSBUF0x99 CLINE29 SBUFequ099h ; end of succession 29 ; succession 30 ; SFRPCON0x87 CLINE30 PCONequ087h ; end of succession 30 ; succession 31 ; CLINE31 ; end of succession 31 ; succession 2 CLINE0 ; end of succession 0 ; succession 1 ; /*float. h CLINE1 ; end of succession 1 ; succession 2 ; CLINE2 ; end of succession 2 ; succession 3 ; Copyright (c) SPJ Systems 1998 CLINE3 ; end of succession 3 ; succession 4 ; All Rights Reserved. CLINE4 ; end of succession 4 ; succession 5 ; */ CLINE5 ; end of succession 5 ; succession 6 ; CLINE6 ; end of succession 6 ; succession 7 ; #define FLT_RADIX2 CLINE7 ; end of succession 7 ; succession 8 ; #define FLT_DIG6 CLINE8 ; end of succession 8 ; succession 9 ; CLINE9 ; end of succession 9 ; succession 10 ; #define FLT_MANT_DIG24 CLINE10 ; end of succession 10 ; succession 11 ; #define FLT_MAX_EXP+128 CLINE11 ; end of succession 11 ; succession 12 #define FLT_MIN_EXP-125 CLINE12 ; end of succession 12 ; succession 13 ; CLINE13 ; end of succession 13 ; succession 3 CLINE0 ; end of succession 0 ; succession 1 ; #definestart_timer0()asmsetbtcon. 4 CLINE1 ; end of succession 1 ; succession 2 ; #definestop_timer0()asmclrtcon. 4 CLINE2 ; end of succession 2 ; succession 3 ; #definestart_timer1()asmsetbtcon. 6 CLINE3 ; end of succession 3 ; succession 4 ; #definestop_timer1()asmclrtcon. 6 CLINE4 ; end of succession 4 ; succession 5 ; #defineex0_edge()asmsetbtcon. 0 CLINE5 ; end of succession 5 ; succession 6 ; #defineex0_level()asmclrtcon. 0 CLINE6 ; end of succession 6 ; succession 7 ; #defineex1_edge()asmsetbtcon. 2 CLINE7 ; end of succession 7 ; succession 8 ; #defineex1_level()asmclrtcon. 2 CLINE8 ; end of succession 8 ; succession 9 ; #defineenable_rx()asmsetbscon. 4 CLINE9 ; end of succession 9 ; succession 10 ; #definedisable_rx()asmclrscon. 4 CLINE10 ; end of succession 10 ; succession 11 ; #defineclr_ti()asmclrscon. 1 CLINE11 ; end of succession 11 ; succession 12 ; #defineclr_ri()asmclrscon. 0 CLINE12 ; end of succession 12 ; succession 13 ; #defineenable_ex0()asmorlie,#81h CLINE13 ; end of succession 13 ; succession 14 ; #defineenable_t0()asmorlie,#82h CLINE14 ; end of succession 14 ; succession 15 ; #defineenable_ex1()asmorlie,#84h CLINE15 ; end of succession 15 ; succession 16 ; #defineenable_t1()asmorlie,#88h CLINE16 ; end of succession 16 ; succession 17 ; #defineenable_ser()asmorlie,#90h CLINE17 ; end of succession 17 succession 18 ; #defineenable_t2()asmorlie,#0a0h CLINE18 ; end of succession 18 ; succession 19 ; #defineenable_all()asmmovie,#0bfh CLINE19 ; end of succession 19 ; succession 20 ; #defineenable()asmsetbie. 7 ; sets solely the MSB CLINE20 ; end of succession 20 ; succession 21 ; #definedisable_ex0()asmanlie,#0feh CLINE21 ; end of succession 21 ; succession 22 ; #definedisable_t0()asmanlie,#0fdh CLINE22 ; end of succession 22 ; succession 23 ; #definedisable_ex1()asmanlie,#0fbh CLINE23 ; end of succession 23 ; succession 24 ; #definedisable_t1()asmanlie,#0f7h CLINE24 ; end of succession 24 ; succession 25 ; #definedisable_ser()asmanlie,#0efh CLINE25 ; end of succession 25 ; succession 26 ; #definedisable_t2()asmanlie,#0dfh CLINE26 end of succession 26 ; succession 27 ; #definedisable_all()asmmovie,#0 CLINE27 ; end of succession 27 ; succession 28 ; #definedisable()asmclrie. 7 ; evidents solely the MSB CLINE28 ; end of succession 28 ; succession 29 ; #defineset_hi_ex0()asmorlip,#1h CLINE29 ; end of succession 29 ; succession 30 ; #defineset_hi_t0()asmorlip,#2h CLINE30 ; end of succession 30 ; succession 31 ; #defineset_hi_ex1()asmorlip,#4h CLINE31 ; end of succession 31 ; succession 32 ; #defineset_hi_t1()asmorlip,#8h CLINE32 ; end of succession 32 ; succession 33 ; #defineset_hi_ser()asmorlip,#10h CLINE33 ; end of succession 33 ; succession 34 ; #defineset_hi_t2()asmorlip,#20h CLINE34 ; end of succession 34 ; succession 35 ; #defineset_lo_ex0()asmanlip,#0feh CLINE35 ; end of succession 35 ; succession 36 ; #defineset_lo_t0()asmanlip,#0fdh CLINE36 ; end of succession 36 ; succession 37 ; #defineset_lo_ex1()asmanlip,#0fbh CLINE37 ; end of succession 37 ; succession 38 ; #defineset_lo_t1()asmanlip,#0f7h CLINE38 ; end of succession 38 ; succession 39 ; #defineset_lo_ser()asmanlip,#0efh CLINE39 ; end of succession 39 ; succession 40 ; #defineset_lo_t2()asmanlip,#0dfh CLINE40 ; end of succession 40 ; succession 41 ; #defineset_double_baud()asmorlpcon,#80h CLINE41 ; end of succession 41 ; succession 42 ; #defineclr_double_baud()asmanlpcon,#7fh CLINE42 ; end of succession 42 ; succession 43 ; #definepowerdown()asmorlpcon,#2 CLINE43 ; end of succession 43 ; succession 44 ; #definego_idle()asmorlpcon,#1 CLINE44 ; end of succession 44 ; succession 45 ; #defineset_t0_mode(gate,c_t,mode)asmorltmod,#((taking * 8) + (c_t * 4) + command) CLINE45 ; end of succession 45 ; succession 46 ; #defineset_t1_mode(gate,c_t,mode)asmorltmod,#(((taking * 8) + (c_t * 4) + command) * 16) CLINE46 ; end of succession 46 ; succession 47 ; #defineset_com_mode(mode,sm2,ren)asmmovscon,#((command * 64) + (sm2 * 32) + (ren * 16)) CLINE47 ; end of succession 47 ; succession 48 ; CLINE48 ; end of succession 48 succession 4 CLINE0 ; end of succession 0 ; succession 1 CLINE1 ; end of succession 1 ; succession 2 ; CLINE2 ; end of succession 2 ; succession 3 ; Copyright (c) SPJ Systems 1998 CLINE3 ; end of succession 3 ; succession 4 ; All Rights Reserved. CLINE4 ; end of succession 4 succession 5 ; */ CLINE5 ; end of succession 5 ; succession 6 ; CLINE6 ; end of succession 6 ; succession 7 ; unsigned char inportb (unsigned int harborid) ; CLINE7 ; end of succession 7 ; succession 8 ; wanting outportb (unsigned int harborid, unsigned int compute) ; CLINE8 ; end of succession 8 ; succession 9 ; unsigned char peekb (unsigned int addr) ; CLINE9 ; end of succession 9 ; succession 10 ; wanting pokeb (unsigned int addr, unsigned int compute) ; CLINE10 ; end of succession 10 ; succession 11 ; wanting set_tcnt (int tnum, unsigned int sum) ; CLINE11 ; end of succession 11 ; succession 12 ; wanting stoppage (int sum) ; CLINE12 ; end of succession 12 ; succession 13 ; wanting stoppage_ms (int sum) ; CLINE13 ; end of succession 13 ; succession 14 unsigned char lo_nibb (unsigned char ch) ; CLINE14 ; end of succession 14 ; succession 15 ; unsigned char hi_nibb (unsigned char ch) ; CLINE15 ; end of succession 15 ; succession 16 ; int getbyte () ; CLINE16 ; end of succession 16 ; succession 17 ; wanting transmitbyte (unsigned char ch) ; CLINE17 ; end of succession 17 ; succession 18 ; int ser_rdy () ; CLINE18 ; end of succession 18 ; succession 19 ; wanting init_ser () ; CLINE19 ; end of succession 19 ; succession 20 ; CLINE20 ; end of succession 20 ; succession 21 ; #defineINT_EXT01 CLINE21 ; end of succession 21 ; succession 22 ; #defineINT_TMR02 CLINE22 ; end of succession 22 ; succession 23 ; #defineINT_EXT13 CLINE23 ; end of succession 23 ; succession 24 ; #defineINT_TMR14 CLINE24 ; end of succession 24 succession 25 ; #defineINT_SER5 CLINE25 ; end of succession 25 ; succession 26 ; #defineINT_TMR26 CLINE26 ; end of succession 26 ; succession 27 ; CLINE27 ; end of succession 27 ; succession 5 CLINE0 ; end of succession 0 ; succession 1 ; /*math. h CLINE1 ; end of succession 1 ; succession 2 ; CLINE2 ; end of succession 2 ; succession 3 ; Copyright (c) SPJ Systems 1998 CLINE3 ; end of succession 3 ; succession 4 ; All Rights Reserved. CLINE4 ; end of succession 4 ; succession 5 ; */ CLINE5 ; end of succession 5 ; succession 6 ; CLINE6 ; end of succession 6 ; succession 7 ; #definepye3. 14285714285714 CLINE7 ; end of succession 7 ; succession 8 ; #definepyex26. 28571428571429 CLINE8 ; end of succession 8 ; succession 9 ; #definepye_2 1. 57142857142857 CLINE9 ; end of succession 9 succession 10 ; #definepyex3_2 4. 71428571428571 CLINE10 ; end of succession 10 ; succession 11 ; #defineLOG20. 30102999566 CLINE11 ; end of succession 11 ; succession 12 ; #defineNLOG20. 69314718056 CLINE12 ; end of succession 12 ; succession 13 ; #defineCONST_M0. 43429 CLINE13 ; end of succession 13 ; succession 14 ; CLINE14 ; end of succession 14 ; succession 15 ; bear sin (bear x) ; CLINE15 ; end of succession 15 ; succession 16 ; bear cos (bear x) ; CLINE16 ; end of succession 16 ; succession 17 ; bear tan (bear x) ; CLINE17 ; end of succession 17 ; succession 18 ; bear asin(bear x) ; CLINE18 ; end of succession 18 ; succession 19 ; bear acos (bear x) ; CLINE19 ; end of succession 19 ; succession 20 ; bear sinh (bear x) ; CLINE20 ; end of succession 20 ; succession 21 ; bear cosh (bear x) ; CLINE21 ; end of succession 21 ; succession 22 ; bear tanh (bear x) ; CLINE22 ; end of succession 22 ; succession 23 ; bear exp (bear x_flval); CLINE23 ; end of succession 23 ; succession 24 ; bear log (bear compute) ; CLINE24 ; end of succession 24 ; succession 25 ; bear log10 (bear compute) ; CLINE25 ; end of succession 25 ; succession 26 ; bear pow (bear x, bear y) ; CLINE26 ; end of succession 26 ; succession 27 ; bear sqrt (bear x) ; CLINE27 ; end of succession 27 ; succession 28 ; bear ceil (bear x) ; CLINE28 ; end of succession 28 ; succession 29 ; bear pedestal (bear x) ; CLINE29 ; end of succession 29 ; succession 30 ; bear fabs (bear x) ; CLINE30 end of succession 30 ; succession 31 ; bear ldexp (bear reckon, int ability) ; CLINE31 ; end of succession 31 ; succession 32 ; bear frexp (bear reckon, int *power) ; CLINE32 ; end of succession 32 ; succession 33 ; bear modf (bear x, bear *ipart) ; CLINE33 ; end of succession 33 ; succession 34 ; bear fmod (bear n1, bear n2) ; CLINE34 ; end of succession 34 ; succession 35 ; CLINE35 ; end of succession 35 ; succession 6 CLINE0 ; end of succession 0 ; succession 1 ; /*stdlib. h CLINE1 ; end of succession 1 ; succession 2 ; CLINE2 ; end of succession 2 ; succession 3 ; Copyright (c) SPJ Systems 1998 CLINE3 ; end of succession 3 ; succession 4 ; All Rights Reserved. CLINE4 ; end of succession 4 ; succession 5 ; */ CLINE5 ; end of succession 5 succession 6 ; CLINE6 ; end of succession 6 ; succession 7 ; bear atof (char *s) ; CLINE7 ; end of succession 7 ; succession 8 ; int atoi (char *s) ; CLINE8 ; end of succession 8 ; succession 9 ; covet int atol (char *s) ; CLINE9 ; end of succession 9 ; succession 10 ; int abs (int n) ; CLINE10 ; end of succession 10 ; succession 11 ; covet int labs (covet int n) ; CLINE11 ; end of succession 11 ; succession 12 ; CLINE12 ; end of succession 12 ; succession 13 ; wanting int2bcd (int compute, char *dest, int ndigits) ; CLINE13 ; end of succession 13 ; succession 14 ; wanting itoa_c31 (int compute, char *dest, int ndigits) ; CLINE14 ; end of succession 14 ; succession 15 ; wanting ui2a_c31 (unsigned int compute, char *dest, int ndigits) ; CLINE15 end of succession 15 ; succession 16 ; wanting ui2bcd (unsigned int compute, char *dest, int ndigits) ; CLINE16 ; end of succession 16 ; succession 17 ; CLINE17 ; end of succession 17 ; succession 18 ; wanting covet2bcd (covet int val, char *dest, int cnt) ; CLINE18 ; end of succession 18 ; succession 19 ; wanting ltoa_c31 (covet int val, char *dest, int cnt) ; CLINE19 ; end of succession 19 ; succession 20 ; CLINE20 ; end of succession 20 ; succession 7 ; #comprise CLINE0 ; end of succession 0 ; succession 1 ; /*etc. h CLINE1 ; end of succession 1 ; succession 2 ; CLINE2 ; end of succession 2 ; succession 3 ; Copyright (c) SPJ Systems 1998 CLINE3 ; end of succession 3 ; succession 4 ; All Rights Reserved. CLINE4 ; end of succession 4 ; succession 5 ; */ CLINE5 end of succession 5 ; succession 6 ; CLINE6 ; end of succession 6 ; succession 7 ; int bcd2int (char *str, int ndigits) ; CLINE7 ; end of succession 7 ; succession 8 ; wanting flot2str (bear compute, char *dest) ; CLINE8 ; end of succession 8 ; succession 9 ; CLINE9 ; end of succession 9 ; succession 8 ; #comprise CLINE0 ; end of succession 0 ; succession 1 ; /*string. h CLINE1 ; end of succession 1 ; succession 2 ; CLINE2 ; end of succession 2 ; succession 3 ; Copyright (c) SPJ Systems 1998 CLINE3 ; end of succession 3 ; succession 4 ; All Rights Reserved. CLINE4 ; end of succession 4 ; succession 5 ; */ CLINE5 ; end of succession 5 ; succession 6 ; CLINE6 ; end of succession 6 ; succession 7 ; char * strcpy (char *dest, char *src) ; CLINE7 ; end of succession 7 ; succession 8 char * strncpy (char *dest, char *src, int maxlen) ; CLINE8 ; end of succession 8 ; succession 9 ; char * strcat (char *dest, char *src) ; CLINE9 ; end of succession 9 ; succession 10 ; int strcmp (char *s1, char *s2) ; CLINE10 ; end of succession 10 ; succession 11 ; unsigned int strlen (char *src) ; CLINE11 ; end of succession 11 ; succession 12 ; char * strlwr (char *s) ; CLINE12 ; end of succession 12 ; succession 13 ; char * strupr (char *s) ; CLINE13 ; end of succession 13 ; succession 14 ; CLINE14 ; end of succession 14 ; succession 15 ; wanting * memset (wanting *s, int c, int n) ; CLINE15 ; end of succession 15 ; succession 16 ; CLINE16 ; end of succession 16 ; succession 9 ; CLINE9 ; end of succession 9 ; succession 10 ; CLINE10 end of succession 10 ; succession 11 CLINE11 ; end of succession 11 ; succession 12 CLINE12 ; end of succession 12 ; succession 13 CLINE13 ; end of succession 13 ; succession 14 CLINE14 ; end of succession 14 ; succession 15 ; CLINE15 ; end of succession 15 ; succession 16 CLINE16 ; end of succession 16 ; succession 17 CLINE17 ; end of succession 17 ; succession 18 ; bear f1,f2,s1,s2; CLINE18 ; end of succession 18 ; succession 19 ; CLINE19 ; end of succession 19 ; succession 20 ; /*************************************************** CLINE20 ; end of succession 20 ; succession 21 ; * Prototype(s) * CLINE21 ; end of succession 21 ; succession 22 ; ***************************************************/ CLINE22 ; end of succession 22 succession 23 ; CLINE23 ; end of succession 23 ; succession 24 CLINE24 ; end of succession 24 ; succession 25 CLINE25 ; end of succession 25 ; succession 26 CLINE26 ; end of succession 26 ; succession 27 CLINE27 ; end of succession 27 ; succession 28 CLINE28 ; end of succession 28 ; succession 29 ; wanting LCD_init(); CLINE29 ; end of succession 29 ; succession 30 ; CLINE30 ; end of succession 30 ; succession 31 ; /*************************************************** CLINE31 ; end of succession 31 ; succession 32 ; * Sources * CLINE32 ; end of succession 32 ; succession 33 ; ***************************************************/ CLINE33 ; end of succession 33 ; succession 34 CLINE34 ; succession 35 ; { CLINE35 _LCD_delay: end of succession 35 ; succession 36 ; unsigned char n; CLINE36 ; end of succession 36 ; succession 37 ; unsigned char i; CLINE37 ; end of succession 37 ; succession 38 CLINE38 pushbp movbp,sp incsp incsp for0: movr1,bp incr1 incr1 [email protected],#0 for_in0: mova,bp adda,#0fdh movr1,a movmyacc,@r1 movr0,#myacc movr1,bp incr1 incr1 mova,@r1 clrc subba,@r0 clra movacc. 0,c [email protected],a mova,myacc jnzfor_ok0 ljmpfor_out0 for_ok0: ; succession 39 ; { CLINE39 ; succession 40 CLINE40 for1: movr1,bp incr1 [email protected],#0 for_in1: movr1,bp incr1 movr0,#myacc mova,@r1 clrc subba,#100 clra movacc. 0,c [email protected],a mova,myacc jnzfor_ok1 ljmpfor_out1 for_ok1: ; succession 41 ; { CLINE41 ; succession 42 asm nop CLINE42 nop ; succession 43 ; } CLINE43 for_inc1: movr1,bp incr1 [email protected] ljmpfor_in1 for_out1: ; succession 44 ; } CLINE44 for_inc0: movr1,bp incr1 incr1 [email protected] ljmpfor_in0 for_out0: ; end of succession 44 ; succession 45 ; CLINE45 ; end of succession 45 ; succession 46 ; } CLINE46 movsp,bp popbp ret ; end of succession 46 ; succession 47 ; CLINE47 ; end of succession 47 ; succession 48 ; CLINE48 ; end of succession 48 ; succession 49CLINE49 ; succession 50 ; { CLINE50 _LCD_command: ; end of succession 50 ; succession 51 CLINE51 pushbp movbp,sp mova,bp adda,#0fdh movr1,a mov160,@r1 ; end of succession 51 ; succession 52 CLINE52 clr P3. 2 ; end of succession 52 ; succession 53 CLINE53 clr p3. 1 ; end of succession 53 succession 54 CLINE54 setb P3. 0 ; end of succession 54 ; succession 55 CLINE55 clr P3. 0 ; end of succession 55 ; succession 56 CLINE56 mova,#01h pushacc lcall_LCD_stoppage decsp ; end of succession 56 ; succession 57 ; } CLINE57 movsp,bp popbp ret ; end of succession 57 ; succession 58 ; CLINE58 ; end of succession 58 ; succession 59 CLINE59 ; succession 60 ; { CLINE60 _LCD_putc: ; end of succession 60 ; succession 61 ; P2 = ascii; CLINE61 pushbp movbp,sp mova,bp adda,#0fdh movr1,a mov160,@r1 ; end of succession 61 ; succession 62 CLINE62 setb P3. 2 ; end of succession 62 ; succession 63 ; asm clr p3. 1 CLINE63 clr p3. 1 ; end of succession 63 ; succession 64 CLINE64 setb P3. 0 ; end of succession 64 ; succession 65 ; asm clr P3. 0 CLINE65